With more electronic devices such as smartphones and wearables becoming compact,, there is an ever-increasing number of components per semiconductor chip. This gives rise to a host of chronic issues regarding heat generation and the leakage of currents, not to mention the growing complexity of the manufacturing process. In order to keep with the Moore’s Law stating that the number of transistors on a microchip doubles every two years, a new research paradigm is now needed.

The CAD & SoC Design Lab led by professor Kang Seokhyeong at the Department of Electrical Engineering, POSTECH, takes note of software-enabled design automation as a solution to overcome the challenge faced by today’s semiconductor industry. The Lab leverages the inference capabilities of deep learning in pursuit of design methodologies that generate the greatest performance while consuming the least amount of power and design time – all without changing the given conditions. Its ultimate research goal is to completely automate this process through software without any human intervention.

Research is currently underway at the Lab on deep learning hardware and ternary circuitry. To achieve deep learning capabilities that demand a great deal of computation work even on mobile devices, researchers are developing hardware that maintains the accuracy of inference outcomes while consuming less power and improving the speed of computation. Unlike the conventional 2-value switch (0 and 1) digital circuitry, ternary logic circuits have the three logic states of 0, 1, and 2. As this increases the amount of information processed per transistor, these 3-value circuits deliver more functionalities under the same size conditions and thus elevate the level of integration.

As system semiconductor technology is progressing at a tremendous speed globally, professor Kang makes it a point to ceaselessly study emerging theories and produce research outcomes. This philosophy as a scientist earned him the ’10-Year Retrospective Most Influential Paper Award’ at the Asia and South Pacific Design Automation Conference hosted in February 2020 in recognition of his commitment made through his 2010 paper to ‘presenting a new paradigm in semiconductor design methodology’. In that same month, one of his students was also honored with the Outstanding Poster Paper Award for research on ‘Modified A* Algorithm for Obstacle-Aware Topological Bus Routing’ at the 27^th Korean Conference on Semiconductors.

At the CAD & SoC Design Lab, half of the team members study design automation while the other half are engaged in real-life design research, which facilitates their mutual collaboration. They also join with overseas research groups and design companies, and such industry-academia research partnerships allow them to frequently conduct research projects that meet the needs of the time. System semiconductor design research lies at the core of the 4^th Industrial Revolution. In line with this emerging trend, the Lab presents new semiconductor designs as well as design paradigms to create methodologies to design high-efficiency, high-performance integrated circuits at lower costs.