My Research Interests and Publications at POSTECH

When I was a PhD student at POSTECH, my research fields are Parallel Architectures and VLSI Design, Routing Algorithm, Distributed Shared Memory System design and Interconnection Networks Simulation.

Routing Algorithm for Parallel Computers
VLSI Design
Routing Controller for Parallel Computers
Network Interface Controller for Parallel Computers
Interconnection Network Simulation
Distributed Shared Memory System Design

Routing Algorithm for Parallel Computers

H.W.Kim, H.S.Lee ,J.Kim, and S.Lee, "Adaptive Virtual Cut-through as a Viable Routing Method," accepted for Journal of Parallel and Distributed Computing, 1998.

Abstract:

Adaptive virtual cut-through switching is considered as a viable alternative to wormhole switching for fast and hardware-efficient inter-processor communication in multicomputers. Computer simulations are used to show that our implementation of a minimal-path fully-adaptive virtual cut-through algorithm outperforms uniform random message distributions and clustered distributions such as matrix transpose. A hardware-efficient implementation of adaptive virtual cut-through has been implemented using a semi-custom-designed router chip that requires only 2.3% more area than a comparable deterministic wormhole router chip. A network interface controller chip, which is crucial to our adaptive virtual cut-through method, has also been designed and is under fabrication.

VLSI Design

Routing Controller for Parallel Computers

The Router Chip is a minimal adaptive router designed for use in the communication networks of parallel computers.

H.W.Kim "Development of a Routing Controller for Parallel Computer Interconnection Networks," MS thesis, Dept. of EE, POSTECH, February 1995.

Router Chip Layout View

Router Chip Specification

Specification	Description
Technology	Samsung 1.0 um CMOS Process (Single-Poly Double Metal)
Size	5mm X 5mm
# of Pins	100 pins
# of Transistors	30140
Power Consumption	800mW
Operation Speed	12.5MHz
VDD	5 Volts
Routing Algorithm	Ams Algorithm

Network Interface Controller for Parallel Computers (ver.1)

The NIC Chip is a processor-network interface controller for an interconnection network based on Ams Adaptive Routing Algorithm.

H.W.Kim, November, 1995.

NIC Chip Layout View

Interconnection Network Simulation

Implementation of Simulator for Various Routing Algorithms in Interconnection Network.

Distributed Shared Memory System Design

Implementation of Distrubuted Shared Memory System.

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E-mail : khw @etri.re.kr