Crypto processor Design
Crypto module Design for the Next Generation IC Card
Information Security
Real
time Hard Disk Security System with a Crypto processorI have interests in the fields of Information Security, especially in designing of Crypto Processor and Next Generation IC Card. When I was a PhD student at POSTECH, my research fields are Parallel Computer Architecture, VLSI Design, Routing Algorithm/ Distributed Shared Memory System design and Interconnection Networks Simulation. If you want to view my previous research areas, click here.
After I have joined the ETRI Research Institute, I have involved in the Crypto Processor Design Project since 1998. In 1999, We have developed a Crypto Processor which performs encryptions and decryptions of data in real-time. The Crypto Processor has a hard-wired SEED and Triple-DES crypto module and 32-bit RISC controller. The hard-wired crypto module makes it possible the Crypto Processor operates in real-time and the 32-bit RISC controller makes it operable other crypto algorithms such as RSA, ECC, DSA and SHA.
Currently, I have designed the ECC(Elliptic Curve Crypto algorithm) and RSA crypto modules for IC Card. My research Interests are as follows:
Crypto processor Design
Crypto module Design for the Next Generation IC Card
Information Security
Real
time Hard Disk Security System with a Crypto processorDesign and implementation of the crypto processor which operates private key(Triple-DES, SEED and KASUMI) crypto algorithms and public key(RSA and ECC) crypto algorithms.
Figure. Photo view of the Crypto Processor
In this project, I have designed the architecture of the crypto processor which has an ARM7TM, private crypto blocks and public key crypto blocks. Since this crypto processor has an ARM7TM, it is programmable, so it executes various applications. And the dedicated private and public key crypto blocks provide high performance for Triple-DES, SEED, KASUMI, RSA and ECC crypto algorithms.
Because this crypto processor has a PCI interface logic and provides high performance on private & public key crypto algorithms, It is applicable to various security applications such as security gateway, router, NIC, SSL crypto engine and storage security, etc.
Design and implementation of the IC Card which has crypto modules. This work has been done at the part of "Next Generation IC Card Project".
In this project, I have implemented the ECC crypto module and involved in the implementation of the RSA crypto module. It is designed with an area and performance trade-offs for application to resource(area & power) restricted environment.
The ETRI Research Institute is trying to make Next Generation IC Card, which has an Open Platform environment and easily programmable. This Next Generatiion IC Card is compabile with Java Card 2.1.
It is also a security enhanced IC Card because of embedded crypto modules. The Crypto modules in the Next Generation IC Card can execute the RSA and ECC crypto algorithms with a high performance.
We have implemented the RSA and ECC Crypto modules and successfully tested the prototype of these crypto modules in September. 2000. Currently, we are optimizing the area and performance of these Crytpo modules and developing the high level application programs. For designing the ECC Crypto modules, we have followed the SEC-2 recommendation.
In these days, I would like to implement the Hyperelliptic curve crypto processor. To make this, I will study about the research papers and algebraic geometry for understanding the HEC and its mathematical backgrounds.
Real time Hard Disk Security System with a Crypto processor
To evaluate the crypto processor, we have developed the Hard Disk Security System(HDSS).
Figure. Photo view of the Real Time Hard Disk Security Board
The HDSS board shown above figure is mainly composed of PCI interface controller, SRAM buffer and Crypto processor. The Altera FPGA chip is used for PCI interface and the ASIC chip which is located at the right upper part of the board is a crypto processor. The HDSS system can achieve data encryption and decryption operations in real-time. Since the performance of PCI interface is maximally 1056Mbps(33MHz X 32bits) and the average access time of the hard disk(Quantum FireBall Ict 15) in our HDSS system is 12 msec, the latency of crypto processor is negligible when we compared with the high latency of the hard disk access time.